Senior Staff Hardware Engineer, Signal and Power Integrity

We AreSynopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. You Are You have spent years deep in the physics of high-speed signaling, where a trace width or a via placement can mean the difference between a chip that works and one that doesn't. Signal and power integrity is not an afterthought for you, it is the foundation, and you have learned that the best IP designs are the ones where SI/PI constraints shape architecture from day one, not get bolted on at tape-out. You are comfortable running SPICE simulations, setting up 3D EM models, and translating what you find into layout rules that a package designer in another time zone can actually use. When a customer asks whether UCIe will close timing in their 2.5D interposer stack, you do not guess, you model it, validate it, and walk them through the tradeoffs with enough clarity that they trust your guidance. You have worked on enough high-speed interfaces to know that every protocol has its quirks, UCIe, HBM, DDR, PCIe, and you know how to adapt your analysis flows without starting from scratch every time. You script when it saves time, you collaborate when it moves the work forward, and you push back when a design decision will create an SI problem six months down the line. At Synopsys, you will work on UCIe IP that is being designed into the next generation of chiplet-based systems, and the analysis you do will directly influence what ships. What You'll Be Doing Drive SI/PI compliance and sign-off for UCIe IP as a core member of the design team, ensuring the IP meets spec across packaging technologies and customer use cases Run SI/PI feasibility studies for current and next-generation UCIe IP using SPICE simulation, 3D electromagnetic field solvers, and power-aware co-simulation tools Build and continuously improve SI/PI analysis flows and sign-off methodologies that support both internal design validation and customer adoption Define layout constraints for UCIe interfaces across 2D and 2.5D packaging technologies, translating simulation results into actionable design rules Develop SI/PI application notes, design guidelines, and reference materials that help customers implement UCIe IP successfully in their own systems Collaborate with design, verification, and customer engineering teams distributed across global sites to align SI/PI requirements with IP architecture and customer needs Serve as the SI/PI technical point of contact for customer engagements, answering questions, reviewing designs, and troubleshooting signal integrity issues in real deployments The Impact You Will Have Shape UCIe IP architecture decisions by providing early SI/PI feedback that influences floorplanning, power delivery, and interface design before tape-out Build customer confidence in Synopsys UCIe IP by delivering robust SI/PI analysis, clear documentation, and responsive technical support during evaluations and production ramps Accelerate customer time-to-market by creating reusable SI/PI flows, validated models, and design guidelines that reduce the guesswork in high-speed chiplet integration Establish Synopsys as the SI/PI leader in the UCIe ecosystem by contributing to industry best practices and enabling successful deployments at lead customers Enable next-generation AI and HPC systems by ensuring that UCIe IP performs reliably at multi-gigabit data rates across diverse packaging and system configurations Reduce design respins and late-stage failures by catching SI/PI issues early through rigorous simulation and validation during the IP development cycle Contribute to Synopsys' mission to lead in the Era of Pervasive Intelligence by delivering the high-speed interconnect IP that powers chiplet-based architectures What You'll Need Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related technical field 8+ years of hands-on experience in signal integrity, power integrity, or high-speed interface design in the semiconductor or systems industry Strong working knowledge of transmission line theory, S-parameters, eye diagrams, and time-domain and frequency-domain analysis techniques Proven experience with SPICE-based circuit simulation tools and 3D electromagnetic field solvers such as HFSS, Ansys SIwave, or similar platforms Solid understanding of high-speed serial interfaces such as UCIe, HBM, DDR, PCIe, or Ethernet, including protocol-level awareness and physical layer design considerations Experience with scripting in Python or Tcl to automate simulation workflows, post-process results, or build analysis tools is a strong plus Familiarity with both Linux and Windows environments for running simulations, managing files, and collaborating across toolchains Who You Are You can take a customer's package stackup, run an SI analysis, and come back with specific layout recommendations, not just a pass/fail verdict You are comfortable presenting SI/PI tradeoffs to architects and design leads who may not live in the frequency domain every day, and you can explain why a decision matters without losing the technical thread You stay organized across multiple simulation runs, customer requests, and internal design reviews without dropping details or missing deadlines You do not wait for perfect data to start analyzing, you work with what you have, document your assumptions, and refine as more information comes in You push back when a design constraint does not make sense from an SI/PI perspective, and you do it in a way that moves the conversation forward instead of shutting it down You are curious about new packaging technologies, simulation methods, and interface standards, and you bring that curiosity into your work without needing to be asked The Team You'll Be Part Of Your recruiter will share more about the team structure and mission during the interview process. Rewards and Benefits We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.