Staff CAD Flow Engineer, Physical Implementation & Sign Off, AI Hardware

Position Description The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life. Tesla's AI Hardware Team is looking for experienced, highly skilled VLSI engineers who enjoy working across the logic, circuit, methodology, and physical design levels. Our physical design team is growing to tackle a wider range of projects, building on our in-house SOC design expertise. This position entails the design, construction and integration of SOCs, IP, circuits, tool flows, and methodologies into systems using advanced technologies - from definition through characterization.  Our AI Hardware engineering team builds and maintains the end-to-end CAD infrastructure that powers tapeout for complex SoC and 3D IC designs. As a Staff CAD Flow Engineer, you will own the development, deployment, and continuous improvement of implementation and signoff flows — from RTL to GDS. You will be at the center of how we scale design productivity and PPA optimization using agentic AI-driven flows.  Responsibilities Build and maintain RTL-to-GDS implementation flows including synthesis, placement, routing, and signoff integration  Own CTS flow development and optimization — tune clock tree strategies to achieve PPA targets across frequency, power, and area  Develop and manage ECO flows — functional ECOs, timing ECOs, and metal-only ECOs — with robust LEC validation at each stage  Set up and validate electrical analysis flows including static/dynamic IR drop, EM, and power analysis integration within the implementation flow  Develop power intent flows — implement and validate UPF/CPF-driven multi-voltage domain strategies through synthesis and P&R  Maintain parasitic extraction flows and ensure correlation between implementation and signoff tools  Build MMMC timing flows — manage corner and mode configuration for setup, hold, and signoff convergence  Integrate physical verification (DRC/LVS) and formal equivalence checking (LEC) as continuous checkpoints within the flow  Develop and deploy agentic AI flows to automate flow execution, detect bottlenecks, triage violations, and drive closure decisions without manual intervention  Evaluate and adopt new EDA tool capabilities — drive tool bring-up, qualification, and regression benchmarking  Requirements Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent work experience  5+ years of CAD flow development and physical implementation experience on complex SoCs  Deep expertise in CTS methodologies and clock architecture optimization for PPA  Hands-on experience with industry P&R and synthesis tools (Innovus, Genus, Fusion Compiler, or equivalent)  Strong command of ECO methodologies — timing, functional, and metal ECO flows through tapeout  Experience building power analysis and power intent flows (UPF/CPF, multi-voltage)  Proficiency with signoff integration — STA, EMIR, DRC/LVS, and parasitic extraction within a unified flow  Ability to develop, deploy, and scale agentic AI flows for design automation and autonomous closure