Principle DFT Engineer

About Marvell Marvell’s semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.  At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.  Your Team, Your Impact As a part of the Connectivity BU DFT team the suitable candidate will work on all aspects of DFT in products catering to the networking domain: DFT architecture and Testability strategy, Flow, Implementation, Verification and post-Si bring up. Marvell's Connectivity Business Unit is the industry-leading provider of high-speed connectivity solutions powering the full range of network infrastructure — from the optics of AI GPU boards to top-of-rack optical fibers and active copper cables in data centers and their fabrics. The BU spans multiple cutting-edge product lines, including Optical Digital Signal Processing (ODSP), Active Electrical Cable (AEC), and Coherent Digital Signal Processing (CDSP), delivering solutions to enterprise, data center, service providers, and cloud customers worldwide. You'll work closely and mentor other DFT team members for DFT features Implementation, Integration and Verification in SoC. You will also have close interaction with Logic Design/Physical design/STA/ATE teams as needed. What You Can Expect Define and drive the DFT architecture and test strategy for complex IPs and SoCs, ensuring robust testability and alignment with product quality, coverage, and manufacturability goals. Lead the implementation and integration of Scan, ATPG, JTAG, MBIST, and Boundary Scan (BSCAN) solutions, ensuring compliance with IEEE 1149.1/1149.6 standards. Develop and deploy DFT features including test structures, IP-level DFT integration, ATPG fault models, test point insertion, coverage optimization, scan insertion, and MBIST implementation at both block and chip levels. Own and execute hierarchical DFT flows across the design hierarchy, from individual IPs through full-chip integration. Implement, validate, and debug DFT/DFX features, ensuring seamless integration with the overall SoC architecture. Generate and validate production test patterns, perform RTL and netlist verification, execute gate-level simulations (zero-delay and SDF-based), and ensure comprehensive test-mode validation. Develop and maintain test timing constraints, including SDC creation, test-mode timing analysis, and support for block- and chip-level STA signoff activities. Utilize industry-standard EDA tools for Scan, ATPG, MBIST, and JTAG implementation, verification, and debug. Collaborate closely with Design, Synthesis, Physical Design, STA, Validation, and Silicon Bring-up teams to resolve DFT-related issues and ensure successful project execution. Drive Post-Silicon bring-up, ATE debug, silicon characterization, and production ramp-up activities, enabling efficient silicon validation and productization. Own DFT deliverables throughout the project lifecycle, ensuring successful execution from architecture definition through tape out, silicon validation, and manufacturing release. Demonstrate strong ownership, accountability, and technical leadership to ensure successful tape out and post-silicon ramp-up of the project. What We're Looking For