Staff DFT ATPG Engineer, AI Hardware

The Tesla AI Hardware team is at the forefront of revolutionizing artificial intelligence through cutting-edge hardware innovation. Comprising brilliant engineers and visionaries, the team designs and develops advanced AI inference chips tailored to accelerate Tesla’s machine learning capabilities. A key part of this effort is Dojo, Tesla's custom supercomputer system built to efficiently train massive neural networks on vast video data from the fleet. The work of Tesla's AI Hardware team powers the neural networks behind Full Self-Driving (FSD), and Tesla humanoid robot, Optimus, pushing the boundaries of computational efficiency and performance. By creating custom silicon and optimized architectures, the team ensures Tesla remains a leader in AI-driven automotive and energy solutions, shaping a future where intelligent machines enhance human life.  Tesla's AI hardware team is seeking a highly motivated ASIC RTL Design Engineer with a specialization in the mathematical and computational aspects of custom AI accelerators. You will focus on designing high-performance, power-efficient RTL for math-intensive components that power our AI training and inference systems. This role emphasizes expertise in tensor operations, matrix computations, and optimized data paths for advanced AI workloads. If you are passionate about pushing the boundaries of low-precision arithmetic, quantization techniques, and hardware acceleration for machine learning, this is your opportunity to contribute to revolutionary AI hardware.  Our Silicon Engineering team delivers silicon that meets production quality targets from first tapeout. As a Staff DFT ATPG Engineer, you will own pattern generation, ATE test program development, and DFT timing closure — from pre-Si ATPG through OSAT deployment — ensuring structural test quality and production efficiency at scale.  Responsibilities Generate production-quality ATPG patterns using Tessent for stuck-at, transition delay, path delay, cell-aware, and small delay defect (SDD) fault models  Achieve and exceed coverage targets (>99% stuck-at, >98% transition) while minimizing pattern count for ATE test time  Debug low coverage areas — X-state sources, blocking logic, untestable faults, and ATPG abort conditions  Understanding and familiarity of hybrid bonding test concepts  Perform gate-level pattern simulation to validate pattern integrity  Support hierarchical and flat ATPG methodologies for multi-million gate SoC designs  Architect and develop comprehensive ATE test programs covering ATPG, MBIST, Repair, Functional, DC, and HSIO  Own NPI silicon bring-up for structural tests — debug and root cause failures to closure  Deploy and optimize test programs at OSATs for yield, quality, reliability, and cost  Develop custom test methods for product-specific requirements and contribute to wafer probe and final test hardware design  Requirements Degree in Electrical Engineering, Computer Engineering, or related field, or equivalent experience  10+ years across ATPG, ATE test development, and DFT timing  Expert-level Tessent proficiency — TestKompress and MemoryBIST  Deep knowledge of fault models: stuck-at, transition, path delay, cell-aware, and SDD  ATE test program development and OSAT deployment experience  SDC constraint development for DFT test modes; timing closure using Tempus  Ability to use agentic AI flows to automate ATPG and ATE test workflows