STA Lead Engineer

Job Responsibilities: -Work in the full STA cycle, from initial constraints validation to final GDS sign-off -Perform STA setup, convergence, reviews, and signoff for multi-mode, multi-voltage SoC and subsystem designs -Manage timing ECOs (DMSA, tweaker, PrimeClosure) and conduct logical equivalence checks (RTL to Netlist) -Validate and debug timing across multiple PVT conditions using tools such as PrimeTime and Tempus -Work closely with RTL, Synthesis, and Physical Design teams to influence floorplanning and CTS strategies for timing-optimized layouts -Partner with design, DFT, synthesis, technology, CAD, and physical implementation teams